中圖分類號：TN915.05 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.256651 中文引用格式： 張子琪，方震，于宗光. 基于Crossbar多端口緩存共享的交換架構(gòu)設(shè)計[J]. 電子技術(shù)應(yīng)用，2025，51(11)：53-58. 英文引用格式： Zhang Ziqi，F(xiàn)ang Zhen，Yu Zongguang. Design of switching architecture with shared multi-port buffers based on crossbar[J]. Application of Electronic Technique，2025，51(11)：53-58.
Design of switching architecture with shared multi-port buffers based on crossbar
Zhang Ziqi，F(xiàn)ang Zhen，Yu Zongguang
The 58th Research Institute of China Electronics Technology Group Corporation
Abstract： With the continuous development of the network and the continuous improvement of data bandwidth, higher requirements have been put forward for key indicators such as switching capacity, forwarding delay, and memory utilization in network devices. This design adopts a switching architecture based on crossbar multi-port cache sharing to achieve the storage, scheduling, sorting, and forwarding of messages. This design uses a shared cache architecture and defines data packets with descriptors, achieving shared queue cache for multiple queues under multiple ports. Each port supports 8 priority queues, realizing orderly scheduling and reducing the blocking problem of multiple queues. In the cache management of multiple SRAMs, a paged linked list method is adopted to achieve dynamic shared cache, improving data access efficiency and reducing forwarding delay. This design has completed FPGA prototype verification on the XCZU3EG verification platform of Xilinx Company, achieving functional verification and performance testing of the multi-port structure. The average port rate reaches 6.08 Gb/s, and the switching delay is controllable.
Key words : shared cache；multi-port；switching architecture；QoS
